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1. general description the PCF85162 is a peripheral device which interfaces to almost any liquid crystal display (lcd) 1 with low multiplex rates. it generates the drive signals for any static or multiplexed lcd containing up to four backplanes and up to 32 segments. it can be easily cascaded for larger lcd applications. the PCF85162 is compatible with most microcontrollers and communicates via the two-line bidirectional i 2 c-bus. communication overheads are minimized by a display ram with auto-incremented addressing, by hardware subaddressing, and by display memory switching (static and duplex drive modes). 2. features and benefits ? single chip lcd controller and driver ? selectable backplane drive configuration: st atic, 2, 3, or 4 backplane multiplexing ? selectable display bias configuration: static, 1 2 , or 1 3 ? internal lcd bias generation with voltage-follower buffers ? 32 segment drives: ? up to sixteen 7-segment numeric characters ? up to eight 14-segment alphanumeric characters ? any graphics of up to 128 elements ? 32 ? 4-bit ram for display data storage ? display memory bank switching in static and duplex drive modes ? versatile blinking modes ? independent supplies possible for lcd and logic voltages ? wide power supply range: from 1.8 v to 5.5 v ? wide logic lcd supply range: ? from 2.5 v for low-threshold lcds ? up to 6.5 v for guest-host lcds and high-threshold twisted nematic lcds ? low power consumption ? 400 khz i 2 c-bus interface ? no external components required ? manufactured in silicon gate cmos process PCF85162 universal lcd driver fo r low multiplex rates rev. 3 ? 16 june 2011 product data sheet 1. the definition of the abbreviations and acronyms used in this data sheet can be found in section 17 .
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 2 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 3. ordering information 4. marking 5. block diagram table 1. ordering information type number package name description version PCF85162t/1 tssop48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1 table 2. marking codes type number marking code PCF85162t/1 PCF85162t fig 1. block diagram of PCF85162 013aaa064 lcd voltage selector clock select and timing blinker timebase oscillator input filters i 2 c-bus controller power-on reset clk sync osc scl sda sa0 backplane outputs display controller bp0 v dd bp2 bp1 bp3 display segment outputs display register output bank select and blink control 32 s0 to s31 a0 a1 a2 PCF85162 lcd bias generator v ss v lcd command decoder write data control display ram 40 4-bit data pointer and auto increment subaddress counter
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 3 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 6. pinning information 6.1 pinning top view. for mechanical details, see figure 26 . fig 2. pinning diagram for tssop48 (PCF85162t) PCF85162t s23 s22 s24 s21 s25 s20 s26 s19 s27 s18 s28 s17 s29 s16 s30 s15 s31 s14 sda s13 scl s12 sync s11 clk s10 v dd s9 osc s8 a0 s7 a1 s6 a2 s5 sa0 s4 v ss s3 v lcd s2 bp0 s1 bp2 s0 bp1 bp3 013aaa065 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 4 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 6.2 pin description table 3. pin description symbol pin type description sda 10 input/output i 2 c-bus serial data line scl 11 input i 2 c-bus serial clock sync 12 input/output cascade synchronization clk 13 input/output clock line v dd 14 supply supply voltage osc 15 input internal oscillator enable a0 to a2 16 to 18 input subaddress inputs sa0 19 input i 2 c-bus address input v ss 20 supply ground supply voltage v lcd 21 supply lcd supply voltage bp0 to bp3 22 to 25 output lcd backplane outputs s0 to s22, s23 to s31 26 to 48, 1 to 9 output lcd segment outputs
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 5 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 7. functional description the PCF85162 is a versatile peripheral de vice designed to interface between any microcontroller to a wide variety of lcd segment or dot matrix displays (see figure 3 ). it can directly drive any static or multiplexed l cd containing up to four backplanes and up to 32 segments. the possible display configurations of the PCF85162 depend on the number of active backplane outputs required. a selection of display configurations is shown in ta b l e 4 . all of these configurations can be implem ented in the typical system shown in figure 4 . [1] 7 segment display has 8 elem ents including the decimal point. [2] 14 segment display has 16 elements including decimal point and accent dot. fig 3. example of displays suitable for PCF85162 table 4. selection of possi ble display configurations number of backplanes icons digits/characters dot matrix/ elements 7-segment [1] 14-segment [2] 4 128 16 8 128 dots (4 ? 32) 39612696dots (3 ? 32) 2648464dots (2 ? 32) 1324232dots (1 ? 32) 7-segment with dot 14-segment with dot and accent 013aaa312 dot matrix
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 6 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates the host microcontroller maintains the 2-line i 2 c-bus communication channel with the PCF85162. the internal oscillator is enabled by connecting pin osc to pin v ss . the appropriate biasing voltages for the multiplexed lcd waveforms are generated internally. the only other connections required to co mplete the syste m are to the power supplies (v dd , v ss , and v lcd ) and the lcd panel chosen for the application. 7.1 power-on reset (por) at power-on the PCF85162 resets to the following starting conditions: ? all backplane and segment outputs are set to v lcd ? the selected drive mode is: 1:4 multiplex with 1 3 bias ? blinking is switched off ? input and output bank selectors are reset ? the i 2 c-bus interface is initialized ? the data pointer and the subaddress counter are cleared (set to logic 0) ? display is disabled remark: do not transfer data on the i 2 c-bus for at least 1 ms after a power-on to allow the reset action to complete. 7.2 lcd bias generator fractional lcd biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between v lcd and v ss . the center impedance is bypassed by switch if the 1 2 bias voltage level for th e 1:2 multiplex drive mode configuration is selected. the lcd voltage can be temperature compensated externally, using the supply to pin v lcd . 7.3 lcd voltage selector the lcd voltage selector coordinates the mult iplexing of the lcd in accordance with the selected lcd drive configuration. the operation of the voltage selector is controlled by the mode-set command from the command decoder. the biasing configurations that apply to the preferred modes of operatio n, together with the biasing characteristics as functions of v lcd and the resulting discrimina tion ratios (d) are given in ta b l e 5 . the resistance of the power lines must be kept to a minimum. fig 4. typical system configuration host micro- processor/ micro- controller t r 2c b sda scl osc 32 segment drives 4 backplanes lcd panel (up to 128 elements) PCF85162 a0 16 15 11 10 14 21 17 18 19 20 a1 a2 sa0 v dd v ss v ss v dd v lcd 013aaa066 r
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 7 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates discrimination is a term which is defined as the ratio of the on and off rms voltage across a segment. it can be thought of as a measurement of contrast. a practical value for v lcd is determined by equating v off(rms) with a defined lcd threshold voltage (v th(off) ), typically when the lcd exhibits approximately 10 % contrast. in the static drive mode a suitable choice is v lcd >3v th(off) . multiplex drive modes of 1:3 and 1:4 with 1 2 bias are possible but the discrimination and hence the contrast ratios are smaller. bias is calculated by , where the values for a are a = 1 for 1 2 bias a = 2 for 1 3 bias the rms on-state voltage (v on(rms) ) for the lcd is calculated with equation 1 : (1) where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode the rms off-state voltage (v off(rms) ) for the lcd is calculated with equation 2 : (2) discrimination is the ratio of v on(rms) to v off(rms) and is determined from equation 3 : (3) table 5. biasing characteristics lcd drive mode number of: lcd bias configuration backplanes levels static 1 2 static 0 1 ? 1:2 multiplex 2 3 1 2 0.354 0.791 2.236 1:2 multiplex 2 4 1 3 0.333 0.745 2.236 1:3 multiplex 3 4 1 3 0.333 0.638 1.915 1:4 multiplex 4 4 1 3 0.333 0.577 1.732 v off rms ?? v lcd ------------------------ - v on rms ?? v lcd ----------------------- - d v on rms ?? v off rms ?? ------------------------ - = 1 1a + ------------ - v on rms ?? a 2 2a n ++ n 1a + ?? 2 ? ----------------------------- - v lcd = v off rms ?? a 2 2a ? n + n 1a + ?? 2 ? ----------------------------- - v lcd = d v on rms ?? v off rms ?? ---------------------- - a 2 2a n ++ a 2 2a ? n + --------------------------- ==
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 8 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates using equation 3 , the discrimination for an lcd drive mode of 1:3 multiplex with 1 2 bias is and the discrimination for an lcd drive mode of 1:4 multiplex with 1 2 bias is . the advantage of these lcd drive modes is a reduction of the lcd full scale voltage v lcd as follows: ? 1:3 multiplex ( 1 2 bias): ? 1:4 multiplex ( 1 2 bias): these compare with when 1 3 bias is used. it should be noted that v lcd is sometimes referred as the lcd operating voltage. 7.3.1 electro-optical performance suitable values for v on(rms) and v off(rms) are dependent on the lcd liquid used. the rms voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel. for any given liquid, there are two threshold values defined. one point is at 10 % relative transmission (at v th(off) ) and the other at 90 % relative transmission (at v th(on) ), see figure 5 . for a good contrast performance, the following rules should be followed: (4) (5) v on(rms) and v off(rms) are properties of the display driver and are affected by the selection of a, n (see equation 1 to equation 3 ) and the v lcd voltage. v th(off) and v th(on) are properties of the lcd liquid and can be provided by the module manufacturer. it is important to match the module properties to those of the driver in order to achieve optimum performance. 3 1.732 = 21 3 ---------- 1.528 = v lcd 6v off rms ?? ? 2.449v off rms ?? == v lcd 43 ? ?? 3 --------------------- - 2.309v off rms ?? == v lcd 3v off rms ?? = v on rms ?? v th on ?? ? v off rms ?? v th off ?? ?
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 9 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates fig 5. electro-optical characteristic: relative transmission curve of the liquid v rms [v] 100 % 90 % 10 % off segment grey segment on segment v th(off) v th(on) relative transmission 013aaa494
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 10 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 7.4 lcd drive mode waveforms 7.4.1 static drive mode the static lcd drive mode is used when a single backplane is provided in the lcd. the backplane (bpn) and segment (sn) drive waveforms for this mode are shown in figure 6 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = v lcd . v state2 (t) = v (sn + 1) (t) ? v bp0 (t). v off(rms) = 0 v. fig 6. static driv e mode waveforms 013aaa207 v ss v lcd v ss v lcd v ss v lcd v lcd ? v lcd ? v lcd v lcd state 1 0 v bp0 sn sn+1 state 2 0 v (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 1 (on) state 2 (off) t fr
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 11 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 7.4.2 1:2 multiplex drive mode when two backplanes are provided in the lcd, the 1:2 multiplex mode applies. the PCF85162 allows the use of 1 2 bias or 1 3 bias in this mode as shown in figure 7 and figure 8 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.791v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.354v lcd . fig 7. waveforms for the 1:2 multiplex drive mode with 1 2 bias 013aaa208 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 2 state 1 v ss v lcd v lcd /2 v ss v ss v lcd v lcd v ss v lcd v lcd v lcd 0 v 0 v v lcd /2 v lcd /2 v lcd /2 ? v lcd ? v lcd ? v lcd /2 ? v lcd /2 sn sn+1 t fr
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 12 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.745v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.333v lcd . fig 8. waveforms for the 1:2 multiplex drive mode with 1 3 bias 013aaa209 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd ? v lcd 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 s n s n+1 t fr v ss v lcd 2v lcd /3 v lcd /3
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 13 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 7.4.3 1:3 multiplex drive mode when three backplanes are provided in the lcd, the 1:3 multiplex drive mode applies, as shown in figure 9 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.638v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.333v lcd . fig 9. waveforms for the 1:3 multiplex drive mode with 1 3 bias 013aaa210 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 (a) waveforms at driver. bp2 sn sn+1 sn+2 t fr v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd v ss v lcd 2v lcd /3 v lcd /3
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 14 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 7.4.4 1:4 multiplex drive mode when four backplanes are provided in the lcd, the 1:4 multiplex drive mode applies as shown in figure 10 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.577v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.333v lcd . fig 10. waveforms for the 1:4 multiplex drive mode with 1 3 bias 013aaa211 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 bp2 (a) waveforms at driver. bp3 sn sn+1 sn+2 sn+3 t fr v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd v ss v lcd 2v lcd /3 v lcd /3
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 15 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 7.5 oscillator 7.5.1 internal clock the internal logic of the PCF85162 and its lcd drive signals are timed either by its internal oscillator or by an exte rnal clock. the internal osc illator is enabled by connecting pin osc to pin v ss . if the internal oscillator is used, the output from pin clk can be used as the clock signal for several PCF85162 in the system that are connected in cascade. 7.5.2 external clock pin clk is enabled as an external clock input by connecting pin osc to v dd . the lcd frame signal frequency is determined by the clock frequency (f clk ). remark: a clock signal must always be supplied to the device; removing the clock may freeze the lcd in a dc state, which is not suitable for the liquid crystal. 7.6 timing the PCF85162 timing controls the internal da ta flow of the device. this includes the transfer of display data from the display ram to the display segment outputs. in cascaded applications, the correct timing relationship between each PCF85162 in the system is maintained by the synchronization signal at pin sync . the timing also generates the lcd frame signal whose frequency is derived from the clock frequency. the frame signal frequency is a fixed division of the clock frequ ency from either the internal or an external clock: 7.7 display register the display register holds the display data while the corresponding multiplex signals are generated. 7.8 segment outputs the lcd drive section includes 32 segment outputs s0 to s31 which should be connected directly to the lcd. the segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display register. when less than 32 segment outputs are required, the unused segment outputs should be left open-circuit. 7.9 backplane outputs the lcd drive section includes four backplane outputs bp0 to bp3 which must be connected directly to the lcd. the backplane output signals are generated in accordance with the selected lcd drive mode. if less than four backplane outputs are required, the unused outputs can be left open-circuit. ? in the 1:3 multiplex drive mode, bp3 carrie s the same signal as bp1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. ? in the 1:2 multiplex drive mode, bp0 and bp2, respectively, bp 1 and bp3 carry the same signals and may also be paired to increase the drive capabilities. f fr f clk 24 ------- =
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 16 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates ? in the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.10 display ram the display ram is a static 32 ? 4-bit ram which stores lcd data. there is a one-to-one correspondence between ? the bits in the ram bitmap and the lcd elements ? the ram columns and the segment outputs ? the ram rows and the backplane outputs. a logic 1 in the ram bitmap indicates the on-state of the corresponding lcd element; similarly, a logic 0 indicates the off-state. the display ram bit map figure 11 shows the rows 0 to 3 which correspond with the backplane outputs bp0 to bp3, and the columns 0 to 31 which correspond with the segment outputs s0 to s31. in multiplexed lcd applications the segment data of the first, second, third, and fourth row of the display ram are time-multiplexed with bp0, bp1, bp2, and bp3 respectively. when display data is transmitted to the pcf8 5162, the display bytes received are stored in the display ram in accordance with the se lected lcd drive mode. the data is stored as it arrives and depending on the current multiple x drive mode the bits are stored singularly, in pairs, triples or quadrupl es. to illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in figure 12 ; the ram filling organization depicted applies equally to other lcd types. the display ram bit map shows the direct re lationship between the display ram addresses and the segment outputs and between the bits in a ram word and the backplane outputs. fig 11. display ram bit map 0 0 1 2 3 1 2 3 4 27 28 29 30 31 display ram addresses/segment outputs (s) columns display ram rows/ backplane outputs (bp) rows 001aac265
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 17 of 46 nxp semiconductors PCF85162 universal lcd driver for low multiplex rates x = data bit unchanged. fig 12. relationship between lcd layout, drive mode, display ram filling order, and display data transmitted over the i 2 c-bus 001aaj646 acbdpf egd msb lsb bdpcadgfe msb lsb abfgecddp msb lsb cba f geddp msb lsb drive mode static 1:2 multiplex 1:3 multiplex 1:4 multiplex lcd segments lcd backplanes display ram filling order transmitted display byte bp0 bp0 bp1 bp0 bp1 bp2 bp1 bp2 bp3 bp0 n c x x x 0 1 2 3 b x x x a x x x f x x x g x x x e x x x d x x x dp x x x n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 rows display ram rows/backplane outputs (bp) byte1 columns display ram address/segment outputs (s) n a b x x 0 1 2 3 f g x x e c x x d dp x x n + 1 n + 2 n + 3 byte1 byte2 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) n b dp c x 0 1 2 3 a d g x f e x x n + 1 n + 2 byte1 byte2 byte3 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) n + 1 n a c b dp 0 1 2 3 f e g d byte1 byte2 byte3 byte4 byte5 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) s n+2 s n+3 s n+1 s n dp a f b g e c d s n+2 s n+1 s n+7 s n s n+3 s n+5 s n+6 s n+4 dp a f b g e c d s n s n+1 s n+2 dp a f b g e c d s n+1 s n dp a f b g e c d
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 18 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates the following applies to figure 12 : ? in static drive mode the eight transmitted data bits are placed in row 0 as one byte. ? in 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0 and 1 as two successive 4-bit ram words. ? in 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as three successive 3-bit ram words, with bit 3 of the third address left unchanged. it is not recommended to use this bit in a displa y because of the difficult addressing. this last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted (see section 7.10.3 ). ? in 1:4 multiplex drive mode, the eight transm itted data bits are placed in quadruples into row 0, 1, 2, and 3 as two successive 4-bit ram words. 7.10.1 data pointer the addressing mechanism for the display ram is realized using the data pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequen ce commences with the initialization of the data pointer by the load-data-pointer command (see ta b l e 1 2 ). following this command, an arriving data byte is stored at the displa y ram address indicated by the data pointer. the filling order is shown in figure 12 . after each byte is stored, the content of the da ta pointer is automatically incremented by a value dependent on the selected lcd drive mode: ? in static drive mode by eight ? in 1:2 multiplex drive mode by four ? in 1:3 multiplex drive mode by three ? in 1:4 multiplex drive mode by two if an i 2 c-bus data access is terminated early then the state of the data pointer is unknown. the data pointer should be re-written prior to further ram accesses. 7.10.2 subaddress counter the storage of display data is determined by the contents of the subaddress counter. storage is allowed only when the content of the subaddress counter matches with the hardware subaddress applied to a0, a1 and a2. the subaddress counter value is defined by the device-select command (see table 13 ). if the content of the subaddress counter and the hardware subaddress do not match then data storage is inhibited but the data pointer is incremented as if data storage ha d taken place. the subaddress counter is also incremented when the data pointer overflows. in cascaded applications each PCF85162 in the cascade must be addressed separately. initially, the first PCF85162 is selected by sending the device-select command matching the first device's hardware subaddress. then the data pointer is set to the preferred display ram address by sending the load-data-pointer command.
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 19 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates once the display ram of the first PCF85162 has been written, the second PCF85162 is selected by sending the device-select comma nd again. this time however the command matches the second device's hardware subaddress. next the load-data-pointer command is sent to select the preferred disp lay ram address of the second PCF85162. this last step is very important because during writing data to the first PCF85162, the data pointer of the second PCF85162 is incremen ted. in addition, the hardware subaddress should not be changed whilst the device is being accessed on the i 2 c-bus interface. 7.10.3 ram writing in 1:3 multiplex drive mode in 1:3 multiplex drive mode, t he ram is written as shown in ta b l e 6 (see figure 12 as well). if the bit at position bp2/s2 would be writ ten by a second byte tr ansmitted, then the mapping of the segment bits would cha nge as illustrated in ta b l e 7 . in the case described in ta b l e 7 the ram has to be written entirely and bp2/s2, bp2/s5, bp2/s8 etc. have to be connected to elements on the display. this can be achieved by a combination of writing and re writing the ram like follows: ? in the first write to the ram, bits a7 to a0 are written. ? in the second write, bits b7 to b0 are writt en, overwriting bits a1 and a0 with bits b7 and b6. ? in the third write, bits c7 to c0 are writte n, overwriting bits b1 and b0 with bits c7 and c6. depending on the method of wr iting to the ram (standard or entire filling by rewriting), some elements remain unused or can be used, but it has to be considered in the module layout process as well as in the driver software design. table 6. standard ram filling in 1:3 multiplex drive mode assumption: bp2/s2, bp2/s5, bp2/s8 etc. are not connected to any elements on the display. display ram bits (rows)/ backplane outputs (bpn) display ram addresses (columns)/segment outputs (sn) 0 1 2 3 4 5 6 7 8 9 : 0 a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 : 1 a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 : 2 a5 a2 - b5 b2 - c5 c2 - d5 : 3 ----------: table 7. entire ram filling by rewriting in 1:3 multiplex drive mode assumption: bp2/s2, bp2/s5, bp2/s8 etc. are connected to elements on the display. display ram bits (rows)/ backplane outputs (bpn) display ram addresses (columns)/segment outputs (sn) 0 1 2 3 4 5 6 7 8 9 : 0 a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 e4 : 1 a6 a3 a0/b6 b3 b0/c6 c3 c0/d6 d3 d0/e6 e3 : 2 a5 a2 b5 b2 c5 c2 d5 d2 e5 e2 : 3 ----------:
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 20 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 7.10.4 output bank selector the output bank selector (see ta b l e 1 4 ) selects one of the four rows per display ram address for transfer to the display register. the actual row selected depends on the particular lcd drive mode in operation and on the instant in the multiplex sequence. ? in 1:4 multiplex mode, all ram addresses of row 0 are selected, these are followed by the contents of row 1, 2, and then 3 ? in 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially ? in 1:2 multiplex mode, rows 0 and 1 are selected ? in static mode, row 0 is selected the PCF85162 includes a ram bank switching fe ature in the static and 1:2 multiplex drive modes. in the static drive mode, the bank-s elect command may request the contents of row 2 to be selected for display instead of the contents of row 0. in the 1:2 multiplex mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. this gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 7.10.5 input bank selector the input bank selector loads display data into the display ram in accordance with the selected lcd drive configuration. display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see ta b l e 1 4 ). the input bank selector functions inde pendently to the output bank selector. 7.11 blinking the display blinking capabilitie s of the PCF85162 are very versatile. the whole display can blink at a frequencies selected by the blink-select command (see ta b l e 1 5 ). the blink frequencies are fractions of the clock freque ncy. the ratio between the clock and blink frequencies depends on the blink mode selected (see ta b l e 8 ). an additional feature is for an arbitrary select ion of lcd elements to blink. this applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. by means of the output bank selector, the displayed ram banks are exchanged with alternate ram banks at the blink frequency. this mode can also be specified by the blink-select command. in the 1:3 and 1:4 multiplex modes, where no al ternative ram bank is available, groups of lcd elements can blink by selectively changing the display ram data at fixed time intervals.
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 21 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates [1] the blink frequency is proporti onal to the clock frequency (f clk ). for the range of the clock frequency see ta b l e 1 9 . the entire display can blink at a frequency other than the nominal blink frequency. this can be effectively performed by resetting and setting the display enable bit e at the required rate using the mode-set command (see ta b l e 11 ). 7.12 command decoder the command decoder identifies command bytes that arrive on the i 2 c-bus. the commands available to the PCF85162 are defined in ta b l e 9 . all available commands carry a continuation bit c in their most significant bit position as shown in figure 18 . when this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. if this bit is reset, it indicates that the command byte is the last in the transfe r. further bytes will be re garded as display data (see ta b l e 1 0 ). table 8. blink frequencies [1] blink mode blink frequency equation off - 1 2 3 f blink f clk 768 --------- - = f blink f clk 1536 ------------ - = f blink f clk 3072 ------------ - = table 9. definition of PCF85162 commands bit position labeled as - is not used. command operation code reference bit 7 6 5 4 3 2 1 0 mode-set c 1 0 - e b m[1:0] ta b l e 11 load-data-pointer c 0 0 p[4:0] ta b l e 1 2 device-select c1100a[2:0] ta b l e 1 3 bank-select c 1 1 1 1 0 i o ta b l e 1 4 blink-select c 1 1 1 0 ab bf[1:0] ta b l e 1 5 table 10. c bit description bit symbol value description 7c continue bit 0 last control byte in the transfer; next byte will be regarded as display data 1 control bytes continue; next byte will be a command too
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 22 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates [1] the possibility to disable the display allows implementation of blinking under external control. [2] not applicable for static drive mode. table 11. mode-set command bit description bit symbol value description 7c0, 1see ta b l e 1 0 6 to 5 - 10 fixed value 4 - - unused 3e display status 0 disabled (blank) [1] 1 enabled 2b lcd bias configuration [2] 0 1 3 bias 1 1 2 bias 1 to 0 m[1:0] lcd drive mode selection 01 static; bp0 10 1:2 multiplex; bp0, bp1 11 1:3 multiplex; bp0, bp1, bp2 00 1:4 multiplex; bp0, bp1, bp2, bp3 table 12. load-data-pointer command bit description bit symbol value description 7c0, 1see ta b l e 1 0 6 to 5 - 00 fixed value 4 to 0 p[4:0] 00000 to 11111 5 bit binary value, 0 to 31; transferred to the data pointer to define one of 32 display ram addresses table 13. device-select command bit description bit symbol value description 7c0, 1see ta b l e 1 0 6 to 3 - 1100 fixed value 2 to 0 a[2:0] 000 to 111 3 bit binary value, 0 to 7; transferred to the subaddress counter to define one of eight hardware subaddresses
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 23 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates [1] the bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. [1] normal blinking is assumed when the lcd multiplex drive modes 1:3 or 1:4 are selected. [2] alternate ram bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. 7.13 display controller the display controller executes the command s identified by the command decoder. it contains the device?s status registers and co ordinates their effects. the display controller is also responsible for loadi ng display data into t he display ram in the correct filling order. table 14. bank-select command bit description bit symbol value description static 1:2 multiplex [1] 7 c 0, 1 see table 10 6 to 2 - 11110 fixed value 1i input bank selection ; storage of arriving display data 0 ram bit 0 ram bits 0 and 1 1 ram bit 2 ram bits 2 and 3 0o output bank selection ; retrieval of lcd display data 0 ram bit 0 ram bits 0 and 1 1 ram bit 2 ram bits 2 and 3 table 15. blink-select command bit description bit symbol value description 7c0, 1see ta b l e 1 0 6 to 3 - 1110 fixed value 2ab blink mode selection 0 normal blinking [1] 1 alternate ram bank blinking [2] 1 to 0 bf[1:0] blink frequency selection 00 off 01 1 10 2 11 3
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 24 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 8. characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) an d a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 8.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see figure 13 ). 8.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 14 ). 8.3 system configuration a device generating a message is a transmit ter; a device receiving a message is the receiver. the device that controls the message is the master, and the devices which are controlled by the master are the slaves (see figure 15 ). fig 13. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 14. definition of start and stop conditions mbc622 sda scl p stop condition sda scl s start condition
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 25 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 8.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlim ited. each byte of eight bits is followed by an acknowledge cycle. ? a slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. ? a master receiver must generate an acknowle dge after the reception of each byte that has been clocked out of the slave transmitter. ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is st able low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). ? a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cl ocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is illustrated in figure 16 . fig 15. system configuration mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig 16. acknowledgement of the i 2 c-bus mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 26 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 8.5 i 2 c-bus controller the PCF85162 acts as an i 2 c-bus slave receiver. it does not initiate i 2 c-bus transfers or transmit data to an i 2 c-bus master receiver. the only data output from the PCF85162 are the acknowledge signals of the selected devices. device selection depends on the i 2 c-bus slave address, on the transferre d command data and on the hardware subaddress. in single device applications, the hardw are subaddress inputs a0, a1, and a2 are normally tied to v ss which defines the hardware subaddress 0. in multiple device applications a0, a1, and a2 are tied to v ss or v dd using a binary coding scheme, so that no two devices with a common i 2 c-bus slave address have the same hardware subaddress. 8.6 input filters to enhance noise immunity in electrical adverse environments, rc low-pass filters are provided on the sda and scl lines. 8.7 i 2 c-bus protocol two i 2 c-bus slave addresses (0111 000 and 0111 001) are used to address the PCF85162. the entire i 2 c-bus slave address byte is shown in ta b l e 1 6 . the PCF85162 is a writ e-only device and will not respond to a read access, therefore bit 0 should always be logic 0. bit 1 of the slave address byte, th at a PCF85162 will respond to, is defined by the level tied to its sa0 input (v ss for logic 0 and v dd for logic 1). having two reserved slave addresses allows the following on the same i 2 c-bus: ? up to 16 PCF85162 for ve ry large lcd applications ? the use of two types of lcd multiplex drive modes the i 2 c-bus protocol is shown in figure 17 . the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by one of two possible PCF85162 slave addresses available. all PCF85162 whose sa0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. this i 2 c-bus transfer is ignored by all PCF85162 whose sa0 inputs are set to the alternative level. table 16. i 2 c slave address byte slave address bit 7 6 5 4 3 2 1 0 msb lsb 011100sa0r/w
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 27 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates after an acknowledgement, one or more command bytes follow, that define the status of each addressed PCF85162. the last command byte sent is identified by resetting its most signif icant bit, continuation bit c, (see figure 18 ). the command bytes are also acknowledged by all addressed PCF85162s on the bus. after the last command byte, one or more display data bytes may follow. display data bytes are stored in the display ram at the ad dress specified by the data pointer and the subaddress counter. both data pointer and subaddress counter are automatically updated and the data directed to the intended PCF85162 device. an acknowledgement, after each byte is asserted, only by the PCF85162s that are addressed via address lines a0, a1, and a2. after the last display byte, the i 2 c-bus master asserts a stop condition (p). alternately a start may be asserted to restart an i 2 c-bus access. fig 17. i 2 c-bus protocol fig 18. format of command byte 013aaa235 s a 0 s 011100 0ac command a p a display data slave address r/w acknowledge by all addressed PCF85162 acknowledge by a0, a1 and a2 selected PCF85162 only 1 byte update data pointers and if necessary, subaddress counter n 1 byte(s) n 0 byte(s) msa833 rest of opcode c msb lsb
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 28 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 9. internal circuitry fig 19. device protection circuits sa0 v dd v dd v ss v ss v lcd v ss sda 001aac269 v ss scl v ss clk v dd v ss osc v dd v ss sync v dd v ss a0, a1, a2 v dd v ss bp0, bp1, bp2, bp3 v lcd v ss s0 to s31 v lcd v ss
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 29 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 10. limiting values [1] pass level; human body model (hbm), according to ref. 6 ? jesd22-a114 ? . [2] pass level; machine model (mm), according to ref. 7 ? jesd22-a115 ? . [3] pass level; charged-device model (cdm), according to ref. 8 ? jesd22-c101 ? . [4] pass level; latch-up testing according to ref. 9 ? jesd78 ? at maximum ambient temperature (t amb(max) ). [5] according to the nxp store and transport requirements (see ref. 11 ? nx3-00092 ? ) the devices have to be stored at a temperature of +8 ? c to +45 ? c and a humidity of 25 % to 75 %. for long term storage products deviant conditions are described in that document. caution static voltages across the liquid crystal display can build up when the lcd supply voltage (v lcd ) is on while the ic supply voltage (v dd ) is off, or vice versa. this may cause unwanted display artifacts. to av oid such artifacts, v lcd and v dd must be applied or removed together. table 17. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.5 v v lcd lcd supply voltage ? 0.5 +7.5 v v i input voltage on each of the pins clk, sda, scl, sync , sa0, osc, a0 to a2 ? 0.5 +6.5 v v o output voltage on each of the pins s0 to s31, bp0 to bp3 ? 0.5 +7.5 v i i input current ? 10 +10 ma i o output current ? 10 +10 ma i dd supply current ? 50 +50 ma i dd(lcd) lcd supply current ? 50 +50 ma i ss ground supply current ? 50 +50 ma p tot total power dissipation - 400 mw p o output power - 100 mw v esd electrostatic discharge voltage hbm [1] - ? 2000 v mm [2] - ? 300 v cdm [3] - ? 1000 v i lu latch-up current [4] - 200 ma t stg storage temperature [5] ? 65 +150 ? c t amb ambient temperature operating device ? 40 +85 ? c
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 30 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 11. static characteristics [1] v lcd > 3 v for 1 3 bias. [2] lcd outputs are open-circuit; inputs at v ss or v dd ; external clock with 50 % duty factor; i 2 c-bus inactive. [3] for typical values, see figure 20 . [4] for typical values, see figure 21 . [5] the i 2 c-bus interface of PCF85162 is 5 v tolerant. [6] i 2 c pins scl and sda have no diode to v dd and when tested may therefore be driven to the v i limiting values given in table 17 (see also figure 19 ). [7] periodically sampled, not 100 % tested. [8] outputs measured one at a time. table 18. static characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 6.5 v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage 1.8 - 5.5 v v lcd lcd supply voltage [1] 2.5 - 6.5 v i dd supply current f clk(ext) = 1536 hz [2] [3] --20 ? a i dd(lcd) lcd supply current f clk(ext) = 1536 hz [2] [4] --60 ? a logic [5] v p(por) power-on reset supply voltage 1.0 1.3 1.6 v v il low-level input voltage on pins clk, sync , osc, a0 to a2, sa0, scl, sda v ss -0.3v dd v v ih high-level input voltage on pins clk, sync , osc, a0 to a2, sa0, scl, sda [6] 0.7v dd -v dd v i ol low-level output current output sink current; v ol = 0.4 v; v dd =5v on pins clk and sync 1- - ma on pin sda 3 - - ma i oh(clk) high-level output current on pi n clk output source current; v oh =4.6v; v dd =5v 1- - ma i l leakage current v i =v dd or v ss ; on pins clk, scl, sda, a0 to a2, and sa0 ? 1- +1 ? a i l(osc) leakage current on pin osc v i =v dd ? 1- +1 ? a c i input capacitance [7] --7pf lcd outputs ? v o output voltage variation on pins bp0 to bp3 and s0 to s31 ? 100 - +100 mv r o output resistance v lcd = 5 v [8] on pins bp0 to bp3 - 1.5 - k ? on pins s0 to s31 - 6.0 - k ?
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 31 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates t amb =30 ? c; 1:4 multiplex drive mode; v lcd = 6.5 v; f clk(ext) = 1.536 khz; all ram written with logic 1; no display connected; i 2 c-bus inactive. fig 20. typical i dd with respect to v dd t amb =30 ? c; 1:4 multiplex drive mode; f clk(ext) = 1.536 khz; all ram written with logic 1; no display connected. fig 21. typical i dd(lcd) with respect to v lcd v dd (v) 26 5 34 001aal523 2 3 1 4 5 i dd ( a) 0 001aal524 v lcd (v) 39 7 5 8 12 4 16 20 i dd(lcd) ( a) 0
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 32 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 12. dynamic characteristics [1] typical output duty factor: 50 % measured at the clk output pin. [2] not tested in production. [3] all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . table 19. dynamic characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 6.5 v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit clock f clk(int) internal clock frequency [1] 1440 1970 2640 hz f clk(ext) external clock frequency 960 - 2640 hz f fr frame frequency internal clock 60 82 110 hz external clock 40 - 110 hz t clk(h) high-level clock time 60 - - ? s t clk(l) low-level clock time 60 - - ? s synchronization t pd(sync_n) sync propagation delay - 30 - ns t sync_nl sync low time 1 - - ? s t pd(drv) driver propagation delay v lcd = 5 v [2] --30 ? s i 2 c-bus [3] pin scl f scl scl clock frequency - - 400 khz t low low period of the scl clock 1.3 - - ? s t high high period of the scl clock 0.6 - - ? s pin sda t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns pins scl and sda t buf bus free time between a stop and start condition 1.3 - - ? s t su;sto set-up time for stop condition 0.6 - - ? s t hd;sta hold time (repeated) start condition 0.6 - - ? s t su;sta set-up time for a repeated start condition 0.6 - - ? s t r rise time of both sda and scl signals f scl = 400 khz - - 0.3 ? s f scl < 125 khz - - 1.0 ? s t f fall time of both sda and scl signals - - 0.3 ? s c b capacitive load for each bus line - - 400 pf t w(spike) spike pulse width on the i 2 c-bus--50ns
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 33 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates fig 22. driver timing waveforms fig 23. i 2 c-bus timing waveforms 013aaa298 t pd(drv) t sync_nl t pd(sync_n) clk sync bpn, sn t clk(h) t clk(l) 1 / f clk 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd 10 % 80 % 10 % sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 34 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 13. application information 13.1 cascaded operation large display configurations of up to 16 PCF85162 can be recognized on the same i 2 c-bus by using the 3-bit hardware subaddress (a0, a1, and a2) and the programmable i 2 c-bus slave address (sa0). when cascaded PCF85162 are synchronized, they can share the backplane signals from one of the devices in the cascade. such an arrangement is cost-effective in large lcd applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. th e other PCF85162 of the cascade contribute additional segment outputs, but their ba ckplane outputs are left open-circuit (see figure 24 ). table 20. addressing cascaded PCF85162 cluster bit sa0 pin a2 pin a1 pin a0 device 100000 0011 0102 0113 1004 1015 1106 1117 210008 0019 01010 01111 10012 10113 11014 11115
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 35 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates the sync line is provided to maintain the corr ect synchronization between all cascaded PCF85162. synchronization is guaranteed after a power-on reset. the only time that sync is likely to be needed is if synchroniz ation is accidentally lost (e.g. by noise in adverse electrical environments or by defi ning a multiplex drive mode when PCF85162 with different sa0 levels are cascaded). sync is organized as an input/output pin. the output selection is realized as an open-drain driver with an internal pull-up resistor. a PCF85162 asserts the sync line at the onset of its last active backplane signal and monitors the sync line at all other times. if synchronization in the cascade is lost, it is restored by the first PCF85162 to assert sync . the timing relationship between the backplane waveforms and the sync signal for the various drive modes of the PCF85162 are shown in figure 25 . the contact resistance between the sync on each cascaded devi ce must be controlled. if the resistance is too high, the device is no t able to synchronize properly; this is particularly applicable to chip-on-glass applications. the maximum sync contact resistance allowed for the number of devices in cascade is given in ta b l e 2 1 . (1) is master (osc connected to v ss ). (2) is slave (osc connected to v dd ). fig 24. cascaded PCF85162 configuration host micro- processor/ micro- controller sda scl clk osc sync 32 segment drives 4 backplanes 32 segment drives lcd panel (up to 2048 elements) PCF85162 a0 a1 a2 sa0 v dd v lcd dd v lcd v 013aaa067 sda scl sync clk osc bp0 to bp3 (open-circuit) a0 a1 a2 sa0 v ss v ss v ss v dd v lcd PCF85162 bp0 to bp3 r t r 2c b (2) (1)
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 36 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates the PCF85162 can always be cascaded with other devices of the same type or conditionally with other devices of the same fa mily. this allows opti mal drive selection for a given number of pixels to display. figure 22 and figure 25 show the timing of the synchronization signals. in a cascaded configuration only one PCF85162 master must be used as clock source. all other PCF85162 in the cascade must be configured as slave such that they receive the clock from the master. table 21. sync contact resistance number of devices maximum contact resistance 26 k ? 3 to 5 2.2 k ? 6 to 10 1.2 k ? 10 to 16 700 ? fig 25. synchronization of the cascade for the various PCF85162 drive modes t fr = f fr 1 bp0 sync bp0 (1/2 bias) sync bp0 (1/3 bias) (a) static drive mode. (b) 1:2 multiplex drive mode. (c) 1:3 multiplex drive mode. (d) 1:4 multiplex drive mode. bp0 (1/3 bias) sync sync bp0 (1/3 bias) mgl755
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 37 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates if an external clock source is used, all pcf85 162 in the cascade must be configured such as to receive the clock from that exte rnal source (pin osc connected to v dd ). thereby it must be ensured that the clock tree is de signed such that on all PCF85162 the clock propagation delay from the clock source to all PCF85162 in the cascade is as equal as possible since otherwise synchronization artefacts may occur. in mixed cascading configurations , care has to be taken that the specifications of the individual cascaded devices are met at all times.
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 38 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 14. package outline fig 26. package outline sot362-1 (tssop48) unit a 1 a 2 a 3 b p cd (1) e (2) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.2 0.1 8 0 o o 0.1 dimensions (mm are the original dimensions). notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. sot362-1 99-12-27 03-02-19 w m a a 1 a 2 d l p q detail x e z e c l x (a ) 3 0.25 124 48 25 y pin 1 index b h 1.05 0.85 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 1 0.25 8.3 7.9 0.50 0.35 0.8 0.4 0.08 0.8 0.4 p e v m a a tssop48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1 a max. 1.2 0 2.5 5 mm scale mo-153
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 39 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 15. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards. 16. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 16.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 40 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 16.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 16.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 27 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 2 2 and 23 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 27 . table 22. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ? c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 23. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ? c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 41 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 17. abbreviations msl: moisture sensitivity level fig 27. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 24. abbreviations acronym description cmos complementary metal-oxide semiconductor cdm charged-device model dc direct current hbm human body model i 2 c inter-integrated circuit ic integrated circuit lcd liquid crystal display mm machine model msl moisture sensitivity level pcb printed-circuit board ram random access memory rc resistance and capacitance rms root mean square scl serial clock line sda serial data line smd surface-mount device
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 42 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 18. references [1] an10365 ? surface mount reflow soldering description [2] an10853 ? esd and emc sensitivity of ic [3] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [4] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [5] ipc/jedec j-std-020d ? moisture/reflow sensitiv ity classification for nonhermetic solid state surface mount devices [6] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [7] jesd22-a115 ? electrostatic discharge (esd) se nsitivity testing machine model (mm) [8] jesd22-c101 ? field-induced charged-device model test method for electrostatic-discharge-withstand thresh olds of microelectronic components [9] jesd78 ? ic latch-up test [10] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [11] nx3-00092 ? nxp store and transport requirements [12] snv-fa-01-02 ? marking formats integrated circuits [13] um10204 ? i 2 c-bus specification and user manual
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 43 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 19. revision history table 25. revision history document id release date data sheet status change notice supersedes PCF85162 v.3 20110616 product data sheet - PCF85162_2 modifications: ? added section 7.10.3 PCF85162_2 20100507 product data sheet - PCF85162_1 PCF85162_1 20100107 product data sheet - -
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 44 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 20.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 20.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
PCF85162 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 16 june 2011 45 of 46 nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 20.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 21. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors PCF85162 universal lcd driver fo r low multiplex rates ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 16 june 2011 document identifier: PCF85162 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 power-on reset (por) . . . . . . . . . . . . . . . . . . 6 7.2 lcd bias generator . . . . . . . . . . . . . . . . . . . . . 6 7.3 lcd voltage selector . . . . . . . . . . . . . . . . . . . . 6 7.3.1 electro-optical performance . . . . . . . . . . . . . . . 8 7.4 lcd drive mode waveforms . . . . . . . . . . . . . . 10 7.4.1 static drive mode . . . . . . . . . . . . . . . . . . . . . . 10 7.4.2 1:2 multiplex drive mode. . . . . . . . . . . . . . . . . 11 7.4.3 1:3 multiplex drive mode. . . . . . . . . . . . . . . . . 13 7.4.4 1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 14 7.5 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5.1 internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.6 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.7 display register . . . . . . . . . . . . . . . . . . . . . . . . 15 7.8 segment outputs. . . . . . . . . . . . . . . . . . . . . . . 15 7.9 backplane outputs . . . . . . . . . . . . . . . . . . . . . 15 7.10 display ram . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.10.1 data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.10.2 subaddress counter . . . . . . . . . . . . . . . . . . . . 18 7.10.3 ram writing in 1:3 multiplex drive mode. . . . . 19 7.10.4 output bank selector . . . . . . . . . . . . . . . . . . . 20 7.10.5 input bank selector . . . . . . . . . . . . . . . . . . . . . 20 7.11 blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.12 command decoder . . . . . . . . . . . . . . . . . . . . . 21 7.13 display controller . . . . . . . . . . . . . . . . . . . . . . 23 8 characteristics of the i 2 c-bus . . . . . . . . . . . . 24 8.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.2 start and stop conditions . . . . . . . . . . . . . 24 8.3 system configuration . . . . . . . . . . . . . . . . . . . 24 8.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.5 i 2 c-bus controller . . . . . . . . . . . . . . . . . . . . . . 26 8.6 input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.7 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 26 9 internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 28 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 29 11 static characteristics. . . . . . . . . . . . . . . . . . . . 30 12 dynamic characteristics . . . . . . . . . . . . . . . . . 32 13 application information . . . . . . . . . . . . . . . . . 34 13.1 cascaded operation. . . . . . . . . . . . . . . . . . . . 34 14 package outline. . . . . . . . . . . . . . . . . . . . . . . . 38 15 handling information . . . . . . . . . . . . . . . . . . . 39 16 soldering of smd packages . . . . . . . . . . . . . . 39 16.1 introduction to soldering. . . . . . . . . . . . . . . . . 39 16.2 wave and reflow soldering. . . . . . . . . . . . . . . 39 16.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 40 16.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 40 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 41 18 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 19 revision history . . . . . . . . . . . . . . . . . . . . . . . 43 20 legal information . . . . . . . . . . . . . . . . . . . . . . 44 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 44 20.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 20.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 44 20.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 45 21 contact information . . . . . . . . . . . . . . . . . . . . 45 22 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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